In the fabrication of integrated circuits and other electronic devices, multiple layers of conducting, semiconducting and dielectric materials are deposited on or removed from a surface of a semiconductor wafer. Thin layers of conducting, semiconducting, and dielectric materials can be deposited by a number of deposition techniques. Common deposition techniques in modern processing include physical vapor deposition (PVD), also known as sputtering, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), and electrochemical plating (ECP).
As layers of materials are sequentially deposited and removed, the uppermost surface of the wafer becomes non-planar. Because subsequent semiconductor processing (e.g., metallization) requires the wafer to have a flat surface, the wafer needs to be planarized. Planarization is useful in removing undesired surface topography and surface defects, such as rough surfaces, agglomerated materials, crystal lattice damage, scratches, and contaminated layers or materials.
Chemical mechanical planarization, or chemical mechanical polishing (CMP), is a common technique used to planarize substrates, such as semiconductor wafers. In conventional CMP, a wafer is mounted on a carrier assembly and positioned in contact with a polishing pad in a CMP apparatus. The carrier assembly provides a controllable pressure to the wafer, pressing it against the polishing pad. The pad is moved (e.g., rotated) relative to the wafer by an external driving force. Simultaneously therewith, a polishing composition (“slurry”) or other polishing solution is provided between the wafer and the polishing pad. Thus, the wafer surface is polished and made planar by the chemical and mechanical action of the pad surface and slurry. However, there is a great deal of complexity involved in CMP. Each type of material requires a unique polishing composition, a properly designed polishing pad, optimized process settings for both polish and post-CMP clean and other factors that must be individually tailored to the application of polishing a particular material.
Chemical mechanical polishing has become a preferred method for polishing tungsten during the formation of tungsten interconnects and contact plugs in integrated circuit designs. Tungsten is frequently used in integrated circuit designs for contact/via plugs. Typically, a contact or via hole is formed through a dielectric layer on a substrate to expose regions of an underlying component, for example, a first level metallization or interconnect. Tungsten is a hard metal and tungsten CMP runs at relatively aggressive settings which poses unique challenges for tungsten CMP. Unfortunately, many CMP slurries used to polish tungsten, because of their aggressive nature, cause corrosion of the tungsten. The corrosion of tungsten is a common side-effect of CMP. During the CMP process the metal polishing slurry that remains on the surface of the substrate continues to corrode the tungsten beyond the effects of the CMP. Sometimes corrosion is desired; however, in most semiconductor processes corrosion is to be reduced or, preferably, inhibited altogether.
Another problem associated with CMP tungsten is, unfortunately, that many CMP slurries used for polishing tungsten cause the problem of over-polishing and dishing resulting in non-uniform or nonplanar surfaces. The term “dishing” refers to excessive (unwanted) removal of metal, such as tungsten, from metal interconnect precursors and other features on semiconductors during CMP, thereby causing unwanted cavities in the tungsten. Dishing is undesirable since, in addition to causing nonplanar surfaces, it negatively affects the electrical performance of the semiconductor. The severity of the dishing can vary but it typically is severe enough to cause erosion of underlying dielectric materials such as silicon dioxide (TEOS). Erosion is undesirable since the dielectric layer should ideally be flawless and free of cavities to endure optimal electrical performance of the semiconductor. Ideally, CMP formulations simultaneously address both the dishing and erosion problems during tungsten polishing; however, CMP formulations may inhibit dishing while failing to address erosion, or sacrifice the inhibition of dishing to prevent erosion.
The topographical defects which can result from such dishing and erosion can further lead to non-uniform removal of additional materials from the substrate surface, such as barrier layer material disposed beneath the conductive material or dielectric material and produce a substrate surface having less than desirable quality which can negatively impact the performance of integrated circuits of the semiconductor. In addition, as features on the surface of semiconductors become more and more miniaturized, it becomes increasingly difficult to successfully polish the surfaces of the semiconductors.
Therefore, there is a need for a CMP method and composition for tungsten which at least inhibits corrosion of tungsten, but, preferably, further simultaneously reduces dishing and erosion.